1. Field of the Invention
The present invention relates to a current sense amplifier for use in a semiconductor memory device and more particularly to such an amplifier capable of performing accurate sensing operations using a low power supply voltage.
2. Description of the Related Art
As the density of semiconductor memory devics increases, operating power supply voltages decrease thereby also reducing current consumption. In the case of, e.g., a dynamic random access memory implemented with CMOS technology, this narrows the range of voltages used to represent one of two binary states. It is desireable, therefore, to provide the most accurate possible sensing to determine the state of a memory cell. Accurate amplification of voltage levels on bit lines is therefore highly desirable. Due to the trend in decreasing power-supply voltages for semiconductor memory devices, it is difficult to sense the voltage difference between complementary voltage levels on a pair of bit lines.
In one prior art semiconductor memory device, after information stored in the memory cell is developed by a bit line sense amplifier, it is transmitted to an input/output (I/O) line. The power supply voltage is proportional to the voltage difference between a pair of bit lines. For low voltage power supplies, the difference between the potentials on the bit lines is also low. This reduces the sensing margin of an I/O line sense amplifier and makes it difficult to determine the state of a line. In order to overcome this difficulty, a current sense amplifier is provided wihich is able to sense current generated by a voltage level developed by a bit line sense amplifier. When using such a current sense amplifier, a pair of sub-I/O lines are connected between a pair of bit lines and a pair of I/O lines. The bit line potential on the sub-I/O lines is used to develop a current which is easily sensed by the current sense amplifier. The current sense amplifier uses the current to generate corresponding voltage levels on the I/O lines. A current sensing circuit utilizing sub-I/O lines is disclosed in papers entitled "A Dynamic Current-Offset Calibration (DCC) Sense Amplifier with Fish-Bone shaped Bit line (FBB) for High Density SRAMs", on pages 115 to 116 of a publication "1994 VLSI Symposium", by J. Takahashi, et al., entitled "A Current Sense-Amplifier for Fast CMOS SRAMs", on pages 71 to 72 of a publication "1990 VLSI Symposium", by E. Seevinck, et al., and entitled "A 9ns 16Mb CMOS SRAM with Offset Reduced Current Sense Amplifier", on pages 248 to 249 of a publication "1993 ISSCC", by K. Seno, et al.
As power supplies continue to provide lower voltages, the threshold voltages of transistors used in a current sense amplifier are high enough so that proper operation of the current sense amplifier is impeded. An example of a prior art current sense amplifier coupled to a core part of a semiconductor memory device is depicted schematically in FIG. 1 with signal wave forms thereof depicted in FIG. 2. The above-described distadvantages associated with the prior art current sense amplifier will become more fully apparent after the following description of the structure and operation of the circuit of FIG. 1.
In FIG. 1, the bit lines BL and nBL (nBL being depicted in the drawing by BL with a bar thereover) are connected to a memory cell array 10. A pair of transistors 12, 14, which are driven by column selection signals CSL, gate bit lines from memory cell 10 onto sub-I/O lines SIO, nSIO, (nSIO being depicted in the drawing by SIO with a bar thereove) respectively. Lines SIO, nSIO are tied to the bit lines via transistors 12, 14 and to the power supply voltage Vet via biasing resistors 28, 30, respectively. Lines SIO, nSIO are connected to input terminals of the current sense amplifier 16, which is designated by dashed lines. Output terminals of sense amplifier 16 are connected to I/O lines IO, nIO.
Current sense amplifier 16 includes PMOS transistors 18, 20 which each have sources connected to the sub-IO lines SIO, nSIO, respectively. Drains of PMOS transistors 18, 20 are connected to those of NMOS transistors 22, 24, respectively. The PMOS transistors include gates which are cross-coupled with the drains of the opposite PMOS transistors. Sources of NMOS transistors 22, 24 are coupled to each other and are also connected in common to a drain of an NMOS transistor 26. The gates of NMOS transistors 22, 24 are connected to their respective drains, thereby forming a diode, which are in common with I/O lines IO, nIO, respectively. NMOS transistor 26 includes a source to which an activating signal Y.sub.SEL is applied to couple the drains of transistors 22, 24 to ground Vss responsive to an activating signal from a column selection circuit (not shown).
A description will now be made of the operation of the prior art circuit of FIG. 1. Memory cell array 10 is of conventional construction and includes a precharge circuit precharging bit lines BL, nBL to a predetermined level, an equivelence circuit for equalizing voltage levels of bit lines BL, nBL, and a bit line sense amplifier for sensing and amplifying the difference between voltage levels appearing on bit lines BL, nBL. Prior to the beginning of a read operation, bit lines BL, nBL are each precharged and equalized to the same voltage level. When a selected memory cell in array 10 is read, a portion of the charge in the memory cell is shared with the charge on bit line BL thereby affecting the potential of bit line BL. This, therefore, generates a voltage difference in the bit lines BL, nBL which were each precharged to an equivalent potential prior to the read operation. This voltage difference may be in the range of several tens to several hundred millivolts.
The voltage difference on bit lines BL, nBL is sensed by the bit line sense amplifier (not shown) in memory cell array 10 which drives the higher voltage to the power supply level and the lower voltage to the Found voltage level. After so doing, the column selection signal CSL transmitted from the column decoder (not shown) is input to columns selection gates 12, 14. With gates 12, 14 thus turned on, the voltage on each of bit lines BL, nBL is transmitted to lines sub-I/O SIO, nSIO.
When an activating signal Y.sub.SEL, generated by conventional column selection circuits (not shown) is transmitted to NMOS transistor 26, current sense amplifier 16 is activated. The sub-I/O lines SIO, nSIO are comprised of the same material and length with both lines being equally loaded. During a read operation one of lines BL, nBL is always high and the other is always low. PMOS transistors 18, 20 are therefore turned on to different states depending upon which of lines SIO, nSIO is high and which is low. The amount of current flowing in each of PMOS transistors 18, 20 is therefore different. Thus, one of the PMOS transistors becomes progressively more turned on while the other becomes progressively more turned off. The difference in the current flowing in each of PMOS transistors 18, 20 causes different currents likewise to flow in NMOS transistors 22, 24. This results in one of lines I/O, nI/O being at a high voltage level and the other being at a low voltage level thereby sensing the current developed by the different potentials on bit lines BL, nB1. The sensed current is associated with a voltage level on lines I/O, nI/O which corresponds to the voltage level on bit lines BL, nBL, respectively. As can be seen in FIG. 2, I/O lines IO, nIO are developed to voltage levels different from each other in accordance with the current change of the sub-I/O lines SIO, nSIO.
Current sense amplifier 16 responds at high speed which is, of course, desireable when reading from a memory. A problem arises, however, when the power supply voltage Vcc is lowered until it approaches the sum of the threshold voltagse of the transistors which are in series with each other in amplifier 16, i.e., PMOS transistor 20 and NMOS transistor 24 in the first leg of the circuit, and PMOS transistor 18 and NMOS transistor 22 in the second leg. For example, if the threshold voltage V.sub.TN of the NMOS transistor is 0.7 volts and the threshold voltage V.sub.TP of the PMOS transistor is 0.7 volts, the power supply voltage should be greater than 1.4 volts. Otherwise, current sense amplifier 16 is in a floating state which impairs its operation. With a low power supply voltage, conductance of the transistors becomes very large and the sensing speed of the current amplifier is thus reduced. In addition, it is difficult to have the same characteristics, such as threshold voltage, for each of the transistors even though all are fabricated in the same process. This results in offset in the response of each of the transistors.